High voltage device and manufacturing method thereof

ABSTRACT

A high voltage device includes: a crystalline silicon layer, a well, a body region, a gate, a source, and a drain. The body region has a P-type conductivity type, and is formed in the well. The gate is located on and in contact with the well. The source and the drain have an N-type conductivity type, and are located below, outside, and at different sides of the gate, and are located in the body region and the well respectively. An inverse region is defined in the body region between the source and the well, to serve as an inverse current channel in an ON operation. The inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*10 13  atoms/cm 2 . Adrift region is defined in the well, between the body region and the drain, to serve as a drift current channel in an ON operation.

CROSS REFERENCES

The present invention claims priority to TW 107134195 filed on Sep. 27,2018.

BACKGROUND OF THE INVENTION Field of Invention

The present invention relates to a high voltage device and amanufacturing method thereof; particularly, it relates to such highvoltage device and manufacturing method which can reduce theon-resistance of the high voltage device.

Description of Related Art

FIGS. 1A and 1B show schematic diagrams of a cross-section view and atop-view of a prior art high voltage device 100, respectively. In thecontext of the present invention, a “high voltage” device refers to adevice which needs to withstand a voltage over 5V on a drain thereof innormal operation. Typically, the high voltage device 100 has a driftregion 12 a (as indicated by the dashed frame shown in FIG. 1B) whichseparates the drain 19 and the body region 16 of the high voltage device100, wherein a lateral length of the drift region 12 a is determinedaccording to the threshold voltage that the high voltage device 100 isdesigned to operate by. As shown in FIGS. 1A and 1B, the high voltagedevice 100 includes: a well 12, an isolation region 13, a drift oxideregion 14, a body region 16, a body contact 16′, a gate 17, a source 18and a drain 19. The well 12 has a conductivity type of N-type, and isformed on a semiconductor substrate 11. The isolation region 13 is alocal oxidation of silicon (LOCOS) structure, for defining a deviceregion 13 a which is an active area for an operation of the high voltagedevice 100. The device region 13 a has a range which is indicated by thebold dashed frame in FIG. 1A. The gate 17 overlays a part of the driftoxidation region 14.

The body region 16 includes an inverse region 15 which is defined in thebody region 16 between the source 18 and an upper area of the well 12(as indicated by the oval dashed frame shown in FIG. 1B). The inverseregion 15 serves as an inverse current channel when the high voltagedevice 100 is in an ON operation. Typically, in the inverse region 15,boron atoms doped in the body region 16 serve as P-type impurities toform the inverse current channel when the high voltage device 100 is inan ON operation (i.e. when the gate 17 is applied with an operationvoltage), thereby providing a path for a conductive current to flowthrough. The detail of the above-mentioned mechanism is well known bythose skilled in the art, so it is not redundantly explained here.Nevertheless, during a thermal process in manufacturing the high voltagedevice 100, these boron atoms may diffuse undesirably due to latticedefects. This can cause an undesirable increase of the length of theinverse current channel, to increase the on-resistance.

In view of above, to overcome the drawback in the prior art, the presentinvention provides a high voltage device which can inhibit theundesirable diffusion of the boron atoms, so as to reduce theon-resistance of the high voltage device.

SUMMARY OF THE INVENTION

From one perspective, the present invention provides a high voltagedevice comprising: a crystalline silicon layer, which is formed on asemiconductor substrate; a well having an N-type conductivity type,which is formed in the crystalline silicon layer; a body region having aP-type conductivity type, which is formed in the well; a gate, which islocated on the well and is in contact with the well; and a source and adrain having the N-type conductivity type, wherein the source and thedrain are located below, outside, and at different sides of the gate,and are located in the body region and the well, respectively; whereinan inverse region is defined in the body region, between the source andthe well; the inverse region serving as an inverse current channel whenthe high voltage device is in an ON operation; wherein the inverseregion includes a germanium distribution region which has a germaniumatom concentration higher than 1*10¹³ atoms/cm²; wherein a drift regionis defined in the well, between the body region and the drain; the driftregion serving as a drift current channel when the high voltage deviceis in the ON operation; wherein the inverse region further includes aboron distribution region; the germanium distribution region beingconfigured to restrict a diffusion area of the boron distributionregion.

From another perspective, the present invention provides a manufacturingmethod of a high voltage device, comprising: forming a crystallinesilicon layer on a semiconductor substrate; forming a well in thecrystalline silicon layer, wherein the well has an N-type conductivitytype; forming a body region in the well, wherein the body region has aP-type conductivity type; forming a gate on and in contact with thewell; and forming a source and a drain having the N-type conductivitytype, wherein the source and the drain are located below, outside, andat different sides of the gate, and are located in the body region andthe well, respectively; wherein an inverse region is defined in the bodyregion, between the source and the well; the inverse region serving asan inverse current channel when the high voltage device is in an ONoperation; wherein the inverse region includes a germanium distributionregion which has a germanium atom concentration higher than 1*10¹³atoms/cm²; wherein a drift region is defined in the well, between thebody region and the drain; the drift region serving as a drift currentchannel when the high voltage device is in the ON operation; wherein theinverse region further includes a boron distribution region; thegermanium distribution region being configured to restrict a diffusionarea of the boron distribution region.

In one embodiment, the high voltage device further comprises: a driftoxide region, which is formed on and in contact with the drift region;wherein at least a part of the drift oxide region is located below andin contact with a part of the gate; wherein the drift oxide regionincludes a local oxidation of silicon (LOCOS) structure, a shallowtrench isolation (STI) structure or a chemical vapor deposition (CVD)oxide structure.

In one embodiment, the high voltage device further comprises: a bodycontact having the P-type conductivity type, which is formed in the bodyregion, wherein the body contact serves as an electrical contact of thebody region.

In one embodiment, the gate includes: a dielectric layer, which isformed on and in contact with the well in a vertical direction; aconductive layer, which is formed on and in contact with the dielectriclayer, and serves as an electrical contact of the gate; and a spacerlayer, which is formed outside of two sidewalls of the conductive layer,and serves as an electrical insulation layer of the gate.

In one embodiment, the step of forming the body region in the wellincludes the steps of: implanting a plurality of germanium atoms in thegermanium distribution region via a first ion implantation process step,so that the germanium distribution region has an amorphous region; afterthe plurality of germanium atoms have been implanted in the germaniumdistribution region, implanting a plurality of boron atoms via a secondion implantation process step, in a part of the well which includes thegermanium distribution region; and after the plurality of boron atomshave been implanted in the well, transforming the germanium distributionregion to a crystalline region via a thermal annealing process, andforming the body region and the inverse region within the body region.

In one embodiment, the amorphous region has a depth smaller than 0.1micrometer.

The objectives, technical details, features, and effects of the presentinvention will be better understood with regard to the detaileddescription of the embodiments below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show a top view and a cross-section view of aconventional high voltage device 100, respectively.

FIG. 2 shows a first embodiment of the present invention.

FIG. 3 shows a second embodiment of the present invention.

FIG. 4 shows a third embodiment of the present invention.

FIG. 5 shows a fourth embodiment of the present invention.

FIGS. 6A-6H show a fifth embodiment of the present invention.

DESCRIPTION OF THE PREFERABLE EMBODIMENTS

The drawings as referred to throughout the description of the presentinvention are for illustration only, to show the interrelations amongthe process steps and the layers, while the shapes, thicknesses, andwidths are not drawn in actual scale.

Please refer to FIG. 2, which shows a first embodiment of the presentinvention. FIG. 2 shows a schematic diagram of a cross-section view of ahigh voltage device 200. As shown in FIG. 2, the high voltage device 200includes a crystalline silicon layer 21′, a well 22, an isolationstructure 23, a drift oxide region 24, a body region 26, a body contact26′, a gate 27, a source 28 and a drain 29.

The crystalline silicon layer 21′ is formed on a semiconductor substrate21 and the crystalline silicon layer 21′ has a top surface 21 a and abottom surface 21 b that is opposite to the top surface 21 a in thevertical direction (as indicated by the direction of the solid arrow inFIG. 2). The semiconductor substrate 21 can be, for example but notlimited to, a P-type conductivity type silicon substrate. Thecrystalline silicon layer 21′, for example, is formed on thesemiconductor substrate 21 by an epitaxial growth process step, or, apart of the semiconductor substrate 21 is used as the crystallinesilicon layer 21′. The crystalline silicon layer 21′ can be formed byany method known to a person having ordinary skill in the art, so thedetails thereof are not redundantly explained here.

Still referring to FIG. 2, the isolation structure 23 is formed on thetop surface 21 a and in contact with the top surface 21 a, for defininga device region 23 a. The isolation structure 23 is not limited to thelocal oxidation of silicon (LOCOS) structure as shown in FIG. 2; forexample, it may be a shallow trench isolation (STI) structure instead.The device region 23 a is an active region of the operation of the highvoltage device 200. The drift oxide region 24 is formed on the topsurface 21 a and in contact with the top surface 21 a, and the driftoxide region 24 is located on the drift region 22 a (as indicated by thedashed frame shown in FIG. 2) within the device region 23 a, and is incontact with the drift region 22 a. At least a part of the drift oxideregion 24 is located below and in contact with a part of the gate 27.The drift oxide region 24 can include, for example but not limited to, alocal oxidation of silicon (LOCOS) structure, a shallow trench isolation(STI) structure or a chemical vapor deposition (CVD) oxide structure.

The well 22 having an N-type conductivity type is formed in thecrystalline silicon layer 21′. The well 22 is located below the topsurface 21 a and in contact with the top surface 21 a in the verticaldirection. The well 22 can be formed by, for example but not limited to,an ion implantation process step which implants N-type conductivity typeimpurities in the crystalline silicon layer 21′ in the form ofaccelerated ions, to form the well 22.

The body region 26 having the P-type conductivity type is formed in thewell 22 within the device region 23 a, and is located below and incontact with the top surface 21 a in the vertical direction. The bodycontact 26′ having the P-type conductivity type is formed in the bodyregion 26, and is located below and in contact with the top surface 21 ain the vertical direction, wherein the body contact 26′ serves as anelectrical contact of the body region 26.

The gate 27 is formed on the top surface 21 a of the crystalline siliconlayer 21′ within the device region 23 a, wherein a part of the well 22is located below and in contact with the gate 27 in the verticaldirection. The gate 27 at least includes: a dielectric layer 271, aconductive layer 272, and a spacer layer 273. The dielectric layer 271is formed on the top surface 21 a and in contact with the top surface 21a, and is in contact with the well 22 in the vertical direction. Theconductive layer 272 is formed on the dielectric layer 271 and incontact with the dielectric layer 271, to serve as an electrical contactof the gate 27. The spacer layer 273 is formed outside of two sidewallsof the conductive layer 272, to serve as an electrical insulation layerof the gate 27.

Still referring to FIG. 2, the source 28 and the drain 29 have theN-type conductivity type. The source 28 and the drain 29 are formedbelow the top surface 21 a and in contact with the top surface 21 a inthe vertical direction within the device region 23 a, and are locatedbelow and outside two sides of the gate 27 respectively. The source 28is located in the body region 26, and the drain 29 is located in thewell 22, at a location near the right side of the gate 27 (i.e., theside that is away from the body region 26). An inverse region 25 isdefined in the body region 26 between the source 28 and the well 22 in achannel direction (indicated by a dashed arrow in FIG. 2), and is incontact with the top surface 21 a, to serve as an inverse currentchannel in an ON operation of the high voltage device 200. A driftregion 22 a is defined in the well 22 between the body region 26 and thedrain 29 in the channel direction, and is in contact with the topsurface 21 a, to serve as a drift current channel in the ON operation ofthe high voltage device 200.

Note that the term “inverse current channel” means thus. Taking thisembodiment as an example, when the high voltage device 200 operates inON operation due to the voltage applied to the gate 27, an inverse layeris formed below the gate 27, between the source 28 and the drift currentchannel, so that a conduction current flows through the region of theinverse layer, which is the inverse current channel known to a personhaving ordinary skill in the art, so the details thereof are notredundantly explained here.

Note that the term “drift current channel” means thus. Taking thisembodiment as an example, the drift current channel refers to a regionwhere the conduction current passes through in a drifting manner whenthe high-voltage device 200 operates in ON operation, which is known toa person having ordinary skill in the art, so the details thereof arenot redundantly explained here.

Note that the top surface 21 a as referred to does not mean a completelyflat plane but refers to the surface of the crystalline silicon layer21′. In the present embodiment, for example, a part of the top surface21 a where the drift oxide region 24 is in contact with has a recessedportion.

Note that the gate 27 includes a dielectric layer 271 in contact withthe top surface 21 a, a conductive layer 272 on the dielectric layer271, and a spacer layer 273 having electrical insulation properties,which is known to a person having ordinary skill in the art, so thedetails thereof are not redundantly explained here.

Note that the above-mentioned “P-type conductivity type” and “N-typeconductivity type” mean that impurities of corresponding conductivitytypes are doped in regions of the high voltage MOS device (for examplebut not limited to the aforementioned well, body region, source anddrain, etc.), so that the regions have the corresponding P-typeconductivity type or the corresponding N-type conductivity type.

In addition, the term “high voltage device” refers to a transistordevice wherein a voltage applied to the drain thereof in normaloperation is higher than a specific voltage, such as 5V. A lateraldistance (i.e., a length of the drift region) between the body region 26and the drain 29 of the high voltage device 200 is determined accordingto the required operation voltage during normal operation, so that thedevice can operate at or higher than the aforementioned specificvoltage, which is known to a person having ordinary skill in the art, sothe details thereof are not redundantly explained here.

In basic implementation of the present invention, the high voltagedevice 200 can include, for example but not limited to, the crystallinesilicon layer 21′, the well 22, the body region 26, the gate 27, thesource 28 and the drain 29. However in one preferred embodiment, thehigh voltage device 200 can further include, for example but not limitedto, the isolation structure 23, the drift oxide region 24 and the bodycontact 26′.

One technical feature of the present invention which is advantageousover the prior art is that, according to the present invention, takingthe embodiment shown in FIG. 2 as an example, the inverse region 25includes a germanium distribution region and a boron distributionregion, and the two distribution regions overlap with each other. Thegermanium distribution region has a germanium atom concentration higherthan 1*10¹³ atoms/cm² and the germanium distribution region isconfigured to restrict a diffusion area of the boron distributionregion. In this embodiment, the steps for forming the body region 26 inthe well 22 include, for example but not limited to: implanting thegermanium atoms in the germanium distribution region via a first ionimplantation process step, so that the germanium distribution region hasan amorphous region; next, after the germanium atoms have been implantedin the germanium distribution region, implanting the boron atoms in apart of the well 22 which includes the germanium distribution region viaa second ion implantation process step; and next, after the boron atomshave been implanted in the well 22, transforming the germaniumdistribution region to a crystalline region via a thermal annealingprocess step and forming the body region 26 and the inverse region 25within the body region 26.

After the germanium atoms have been implanted in the germaniumdistribution region, because the germanium atom has a size greater thanthe silicon atom, the silicon atoms in crystalline form will be collidedby the germanium atoms to become amorphous form. Subsequently, the boronatoms are implanted into the amorphous well 22 (which includes thegermanium distribution region), and the amorphous body region 26 istransformed to a crystalline body region 26 (i.e., a re-crystallizedbody region 26) via a thermal annealing process step which for examplecan be the same thermal annealing process step adopted to form thespacer layer 273. Because of the existence of the germanium atoms, there-crystallized silicon-germanium lattices, as compared to the siliconlattices without any germanium atoms, can achieve much bettercrystallization more rapidly. In other words, according to the presentinvention, because the body region 26 formed during the thermalannealing process step has less defects, as compared to the prior artwhere no implantation of the germanium atoms is carried out, thediffusion area of the boron atoms caused by the thermal annealingprocess step can be restricted, to better control the area of theinverse region 25.

In the prior art, taking the high voltage device 100 shown in FIG. 1 asan example, although the silicon lattices of the prior art high voltagedevice 100 can be re-crystallized during the thermal annealing processstep, because there is no existence of the germanium atoms, therecrystallization of the prior art high voltage device 100 is slowerthan the present invention. Generally, in the present invention, ittakes simply several micro-seconds for the silicon-germanium lattices ofthe high voltage device to be re-crystallized to form perfectcrystallization. In contrast, in the prior art, it requires severalseconds for the silicon lattices of the high voltage device to bere-crystallized to form perfect crystallization. As a result, in theprior art, because it takes longer time for the recrystallization,during the thermal annealing process step, the boron atoms diffusefarther along the defects in the silicon lattices; consequently andundesirably, the inverse region 15 becomes larger, resulting in a longerinverse current channel which causes a higher on-resistance and a sloweroperation speed. The present invention can reduce the on-resistance ofthe high voltage device, thereby improving the operation speed of thehigh voltage device.

Please refer to FIG. 3, which shows a second embodiment of the presentinvention. FIG. 3 shows a schematic diagram of a cross-section view of ahigh voltage device 300. As shown in FIG. 3, the high voltage device 300includes a crystalline silicon layer 31′, a well 32, an isolationstructure 33, a drift oxide region 34, a body region 36, a body contact36′, a gate 37, a source 38 and a drain 39.

The crystalline silicon layer 31′ is formed on a semiconductor substrate31 and the crystalline silicon layer 31′ has a top surface 31 a and abottom surface 31 b that is opposite to the top surface 31 a in thevertical direction (as indicated by the direction of the solid arrow inFIG. 3). The semiconductor substrate 31 can be, for example but notlimited to, a P-type conductivity type silicon substrate. Thecrystalline silicon layer 31′, for example, is formed on thesemiconductor substrate 31 by an epitaxial growth process step, or, apart of the semiconductor substrate 31 is used as the crystallinesilicon layer 31′. The crystalline silicon layer 31′ can be formed byany method known to a person having ordinary skill in the art, so thedetails thereof are not redundantly explained here.

Still referring to FIG. 3, the isolation structure 33 is formed on thetop surface 31 a and in contact with the top surface 31 a, for defininga device region 33 a. The isolation structure 33 is not limited to thelocal oxidation of silicon (LOCOS) structure as shown in FIG. 3; forexample, it may be a shallow trench isolation (STI) structure instead.The device region 33 a is an active region of the operation of the highvoltage device 300. The drift oxide region 34 is formed on the topsurface 31 a and in contact with the top surface 31 a, and the driftoxide region 34 is located on the drift region 32 a (as indicated by thedashed frame shown in FIG. 3) within the device region 33 a, and is incontact with the drift region 32 a.

The well 32 having an N-type conductivity type is formed in thecrystalline silicon layer 31′. The well 32 is located below the topsurface 31 a and in contact with the top surface 31 a in the verticaldirection. The well 32 can be formed by, for example but not limited to,an ion implantation process step which implants N-type conductivity typeimpurities in the crystalline silicon layer 31′ in the form ofaccelerated ions, to form the well 32.

The body region 36 having the P-type conductivity type is formed in thewell 32 within the device region 33 a, and is located below and incontact with the top surface 31 a in the vertical direction. The bodycontact 36′ having the P-type conductivity type is formed in the bodyregion 36, and is located below and in contact with the top surface 31 ain the vertical direction, wherein the body contact 36′ serves as anelectrical contact of the body region 36.

The gate 37 is formed on the top surface 31 a of the crystalline siliconlayer 31′ within the device region 33 a, wherein a part of the well 32is located below and in contact with the gate 37 in the verticaldirection. The gate 37 at least includes: a dielectric layer 371, aconductive layer 372, and a spacer layer 373. The dielectric layer 371is formed on the top surface 31 a and in contact with the top surface 31a, and is in contact with the well 32 in the vertical direction. Theconductive layer 372 is formed on the dielectric layer 371 and incontact with the dielectric layer 371, to serve as an electrical contactof the gate 37. The spacer layer 373 is formed outside of two sidewallsof the conductive layer 372, to serve as an electrical insulation layerof the gate 37.

Still referring to FIG. 3, the source 38 and the drain 39 have theN-type conductivity type. The source 38 and the drain 39 are formedbelow the top surface 31 a and in contact with the top surface 31 a inthe vertical direction within the device region 33 a, and are locatedbelow and outside two sides of the gate 37 respectively. The source 38is located in the body region 36, and the drain 39 is located in thewell 32, at a location near the right side of the gate 37 (i.e., theside that is away from the body region 36). An inverse region 35 isdefined in the body region 36 between the source 38 and the well 32 in achannel direction (indicated by a dashed arrow in FIG. 3), and is incontact with the top surface 31 a, to serve as an inverse currentchannel in an ON operation of the high voltage device 300. A driftregion 32 a is defined in the well 32 between the body region 36 and thedrain 39 in the channel direction, and is in contact with the topsurface 31 a, to serve as a drift current channel in the ON operation ofthe high voltage device 300.

In the embodiment shown in FIG. 3, the inverse region 35 includes agermanium distribution region and a boron distribution region, and thetwo distribution regions overlap with each other. The germaniumdistribution region has a germanium atom concentration higher than1*10¹³ atoms/cm² and the germanium distribution region is configured torestrict a diffusion area of the boron distribution region. In thisembodiment, the steps for forming the body region 36 in the well 32include, for example but not limited to, implanting the germanium atomsin the germanium distribution region via a first ion implantationprocess step, so that the germanium distribution region has an amorphousregion; next, after the germanium atoms have been implanted in thegermanium distribution region, implanting the boron atoms in a part ofthe well 32 which includes the germanium distribution region via asecond ion implantation process step; and next, after the boron atomshave been implanted in the well 32, transforming the germaniumdistribution region to a crystalline region via a thermal annealingprocess step and forming the body region 36 and the inverse region 35within the body region 36.

This embodiment differs from the first embodiment in that: the driftoxide region 24 of the first embodiment is a LOCOS structure, while thedrift oxide region 34 of this embodiment is a chemical vapor deposition(CVD) oxide structure. The CVD oxide structure is formed by a CVDdeposition process step. CVD deposition is well known to a person havingordinary skill in the art, so the details thereof are not redundantlyexplained here.

Please refer to FIG. 4, which shows a third embodiment of the presentinvention. FIG. 4 shows a schematic diagram of a cross-section view of ahigh voltage device 400. As shown in FIG. 4, the high voltage device 400includes a crystalline silicon layer 41′, a well 42, an isolationstructure 43, a drift oxide region 44, a body region 46, a body contact46′, a gate 47, a source 48 and a drain 49.

The crystalline silicon layer 41′ is formed on a semiconductor substrate41 and the crystalline silicon layer 41′ has a top surface 41 a and abottom surface 41 b that is opposite to the top surface 41 a in thevertical direction (as indicated by the direction of the solid arrow inFIG. 4). The semiconductor substrate 41 can be, for example but notlimited to, a P-type conductivity type silicon substrate. Thecrystalline silicon layer 41′, for example, is formed on thesemiconductor substrate 41 by an epitaxial growth process step, or, apart of the semiconductor substrate 41 is used as the crystallinesilicon layer 41′. The crystalline silicon layer 41′ can be formed byany method known to a person having ordinary skill in the art, so thedetails thereof are not redundantly explained here.

Still referring to FIG. 4, the isolation structure 43 is formed on thetop surface 41 a and in contact with the top surface 41 a, for defininga device region 43 a. The isolation structure 43 is not limited to thelocal oxidation of silicon (LOCOS) structure as shown in FIG. 4; forexample, it may be a shallow trench isolation (STI) structure instead.The device region 43 a is an active region of the operation of the highvoltage device 400. The drift oxide region 44 is formed on the topsurface 31 a and in contact with the top surface 41 a, and the driftoxide region 44 is located on the drift region 42 a (as indicated by thedashed frame shown in FIG. 4) within the device region 43 a, and is incontact with the drift region 42 a.

The well 42 having an N-type conductivity type is formed in thecrystalline silicon layer 41′. The well 42 is located below the topsurface 41 a and in contact with the top surface 41 a in the verticaldirection. The well 42 can be formed by, for example but not limited to,an ion implantation process step which implants N-type conductivity typeimpurities in the crystalline silicon layer 41′ in the form ofaccelerated ions, to form the well 42.

The body region 46 having the P-type conductivity type is formed in thewell 42 within the device region 43 a, and is located below and incontact with the top surface 41 a in the vertical direction. The bodycontact 46′ having the P-type conductivity type is formed in the bodyregion 46, and is located below and in contact with the top surface 41 ain the vertical direction, wherein the body contact 46′ serves as anelectrical contact of the body region 46.

The gate 47 is formed on the top surface 41 a of the crystalline siliconlayer 41′ within the device region 43 a, wherein a part of the well 42is located below and in contact with the gate 47 in the verticaldirection. The gate 47 at least includes: a dielectric layer 471, aconductive layer 472, and a spacer layer 473. The dielectric layer 471is formed on the top surface 41 a and in contact with the top surface 41a, and is in contact with the well 42 in the vertical direction. Theconductive layer 472 is formed on the dielectric layer 471 and incontact with the dielectric layer 471, to serve as an electrical contactof the gate 47. The spacer layer 473 is formed outside of two sidewallsof the conductive layer 472, to serve as an electrical insulation layerof the gate 47.

Still referring to FIG. 4, the source 48 and the drain 49 have theN-type conductivity type. The source 48 and the drain 49 are formedbelow the top surface 41 a and in contact with the top surface 41 a inthe vertical direction within the device region 43 a, and are locatedbelow and outside two sides of the gate 47 respectively. The source 48is located in the body region 46, and the drain 49 is located in thewell 42, at a location near the right side of the gate 47 (i.e., theside that is away from the body region 46). An inverse region 45 isdefined in the body region 46 between the source 48 and the well 42 in achannel direction (indicated by a dashed arrow in FIG. 4), and is incontact with the top surface 41 a, to serve as an inverse currentchannel in an ON operation of the high voltage device 400. A driftregion 42 a is defined in the well 42 between the body region 46 and thedrain 49 in the channel direction, and is in contact with the topsurface 41 a, to serve as a drift current channel in the ON operation ofthe high voltage device 400.

In the embodiment shown in FIG. 4, the inverse region 45 includes agermanium distribution region and a boron distribution region, and thetwo distribution regions overlap with each other. The germaniumdistribution region has a germanium atom concentration higher than1*10¹³ atoms/cm² and the germanium distribution region is configured torestrict a diffusion area of the boron distribution region. In thisembodiment, the steps for forming the body region 46 in the well 42include, for example but not limited to, implanting the germanium atomsin the germanium distribution region via a first ion implantationprocess step, so that the germanium distribution region has an amorphousregion; next, after the germanium atoms have been implanted in thegermanium distribution region, implanting the boron atoms in a part ofthe well 42 which includes the germanium distribution region via asecond ion implantation process step; and next, after the boron atomshave been implanted in the well 42, transforming the germaniumdistribution region to a crystalline region via a thermal annealingprocess step and forming the body region 46 and the inverse region 45within the body region 46.

This embodiment differs from the first embodiment in that: the driftoxide region 24 of the first embodiment is a LOCOS structure, while thedrift oxide region 44 of this embodiment is a shallow trench isolation(STI) structure. The STI structure is well known to a person havingordinary skill in the art, so the details thereof are not redundantlyexplained here.

Please refer to FIG. 5, which shows a fourth embodiment of the presentinvention. FIG. 5 shows a schematic diagram of a cross-section view of ahigh voltage device 500. As shown in FIG. 5, the high voltage device 500includes a crystalline silicon layer 51′, a well 52, an isolationstructure 53, a body region 56, a body contact 56′, a gate 57, a source58 and a drain 59.

The crystalline silicon layer 51′ is formed on a semiconductor substrate51 and the crystalline silicon layer 51′ has a top surface 51 a and abottom surface 51 b that is opposite to the top surface 51 a in thevertical direction (as indicated by the direction of the solid arrow inFIG. 5). The semiconductor substrate 51 can be, for example but notlimited to, a P-type conductivity type silicon substrate. Thecrystalline silicon layer 51′, for example, is formed on thesemiconductor substrate 51 by an epitaxial growth process step, or, apart of the semiconductor substrate 51 is used as the crystallinesilicon layer 51′. The crystalline silicon layer 51′ can be formed byany method known to a person having ordinary skill in the art, so thedetails thereof are not redundantly explained here.

Still referring to FIG. 5, the isolation structure 53 is formed on thetop surface 51 a and in contact with the top surface 51 a, for defininga device region 53 a. The isolation structure 43 is not limited to thelocal oxidation of silicon (LOCOS) structure as shown in FIG. 5; forexample, it may be a shallow trench isolation (STI) structure instead.The device region 53 a is an active region of the operation of the highvoltage device 500.

The well 52 having an N-type conductivity type is formed in thecrystalline silicon layer 51′. The well 52 is located below the topsurface 51 a and in contact with the top surface 51 a in the verticaldirection. The well 52 can be formed by, for example but not limited to,an ion implantation process step which implants N-type conductivity typeimpurities in the crystalline silicon layer 51′ in the form ofaccelerated ions, to form the well 52.

The body region 56 having the P-type conductivity type is formed in thewell 52 within the device region 53 a, and is located below and incontact with the top surface 51 a in the vertical direction. The bodycontact 56′ having the P-type conductivity type is formed in the bodyregion 56, and is located below and in contact with the top surface 51 ain the vertical direction, wherein the body contact 56′ serves as anelectrical contact of the body region 56.

The gate 57 is formed on the top surface 51 a of the crystalline siliconlayer 51′ within the device region 53 a, wherein a part of the well 52is located below and in contact with the gate 57 in the verticaldirection. The gate 57 at least includes: a dielectric layer 571, aconductive layer 572, and a spacer layer 573. The dielectric layer 571is formed on the top surface 51 a and in contact with the top surface 51a, and is in contact with the well 52 in the vertical direction. Theconductive layer 572 is formed on the dielectric layer 571 and incontact with the dielectric layer 571, to serve as an electrical contactof the gate 57. The spacer layer 573 is formed outside of two sidewallsof the conductive layer 572, to serve as an electrical insulation layerof the gate 57.

Still referring to FIG. 5, the source 58 and the drain 59 have theN-type conductivity type. The source 58 and the drain 59 are formedbelow the top surface 51 a and in contact with the top surface 51 a inthe vertical direction within the device region 53 a, and are locatedbelow and outside two sides of the gate 57 respectively. The source 58is located in the body region 56, and the drain 59 is located in thewell 52, at a location near the right side of the gate 57 (i.e., theside that is away from the body region 56). An inverse region 55 isdefined in the body region 56 between the source 58 and the well 52 in achannel direction (indicated by a dashed arrow in FIG. 5), and is incontact with the top surface 51 a, to serve as an inverse currentchannel in an ON operation of the high voltage device 500. A driftregion 52 a is defined in the well 52 between the body region 56 and thedrain 59 in the channel direction, and is in contact with the topsurface 51 a, to serve as a drift current channel in the ON operation ofthe high voltage device 500.

In the embodiment shown in FIG. 5, the inverse region 55 includes agermanium distribution region and a boron distribution region, and thetwo distribution regions overlap with each other. The germaniumdistribution region has a germanium atom concentration higher than1*10¹³ atoms/cm² and the germanium distribution region is configured torestrict a diffusion area of the boron distribution region. In thisembodiment, the steps for forming the body region 56 in the well 52include, for example but not limited to, implanting the germanium atomsin the germanium distribution region via a first ion implantationprocess step, so that the germanium distribution region has an amorphousregion; next, after the germanium atoms have been implanted in thegermanium distribution region, implanting the boron atoms in a part ofthe well 52 which includes the germanium distribution region via asecond ion implantation process step; and next, after the boron atomshave been implanted in the well 52, transforming the germaniumdistribution region to a crystalline region via a thermal annealingprocess step and forming the body region 56 and the inverse region 55within the body region 56.

This embodiment differs from the first embodiment in that: the driftoxide region 24 of the first embodiment is a LOCOS structure; however,the high voltage device 500 of this embodiment does not include anydrift oxide region on the drift region 52 a. The lateral distance (i.e.,a length of the drift region 52 a) between the body region 56 and thedrain 59 of the high voltage device 500 is determined according to theoperation voltage that the high voltage device is designed to operatewith.

Please refer to FIGS. 6A to 6H, which show a fifth embodiment of thepresent invention. This embodiment shows schematic diagrams of amanufacturing method of the high voltage device 200 according to thepresent invention. FIG. 6B shows a schematic diagram of a cross-sectionview taken along the A-A′ cross-section line shown in FIG. 6A. As shownin FIGS. 6A and 6B, first, a crystalline silicon layer 21′ is formed onthe semiconductor substrate 21, wherein the crystalline silicon layer21′ has a top surface 21 a and a bottom surface 21 b that is opposite tothe top surface 21 a in the vertical direction (as indicated by thedirection of the solid arrow in FIG. 6B). The semiconductor substrate 21is, for example but not limited to, a P-type conductivity type siliconsemiconductor substrate. The crystalline silicon layer 21′, for example,is formed on the semiconductor substrate 21 by an epitaxial growthprocess step, or a part of the semiconductor substrate 21 is used as thecrystalline silicon layer 21′. The crystalline silicon layer 21′ can beformed by any method known to a person having ordinary skill in the art,so the details thereof are not redundantly explained here.

Still referring to FIGS. 6A and 6B, next, an isolation structure 23 anda drift oxide region 24 are formed on and in contact with the topsurface 21 a. The isolation structure 23 is for defining the deviceregion 23 a (as indicated by a dashed frame shown in FIG. 6A). Theisolation structure 23 is not limited to the local oxidation of silicon(LOCOS) structure as shown in the figure; for example, it may be ashallow trench isolation (STI) structure instead. The device region 23 ais an active region of the operation of the high voltage device 200. Thedrift oxide region 24 is formed on the top surface 21 a and in contactwith the top surface 21 a, and the drift oxide region 24 is located onthe drift region 22 a (as indicated by the dashed frame shown in FIG. 2)within the device region 23 a, and is in contact with the drift region22 a.

Next, referring to FIG. 6C, a well 22 having an N-type conductivity typeis formed in the crystalline silicon layer 21′. The well 22 is locatedbelow the top surface 21 a and in contact with the top surface 21 a inthe vertical direction. The well 22 can be formed by, for example butnot limited to, an ion implantation process step which implants N-typeconductivity type impurities in the crystalline silicon layer 21′ in theform of accelerated ions as indicated by dashed arrows shown in FIG. 6C,to form the well 22.

Next, referring to FIG. 6D, a photoresist layer 261 is formed as a maskvia, for example but not limited to, a lithography process step. Next,the germanium atoms are implanted in a germanium distribution region 26a via a first ion implantation process step (as indicated by dashedarrows shown in FIG. 6D), so that the germanium distribution region 26 ahas an amorphous region. The thus formed germanium distribution region26 a has a germanium atom concentration higher than 1*10¹³ atoms/cm². Inone embodiment, preferably, the germanium distribution region 26 a has adepth smaller than, for example but not limited to, 0.1 micrometer. Inone embodiment, more preferably, the range of the germanium distributionregion 26 a encompasses a range from the top surface 21 a downward to adepth of 0.03 micrometer in the vertical direction.

Next, referring to FIG. 6E, after the germanium atoms have beenimplanted in the germanium distribution region 26 a, in one embodiment,the photoresist layer 261 is still used as a mask, and the boron atomsare implanted in a boron distribution region 26 b in a part of the well22 which includes the germanium distribution region 26 a via a secondion implantation process step (as indicated by dashed arrows shown inFIG. 6E).

The inverse region 25 includes a germanium distribution region 26 a anda boron distribution region 26 b, and the two distribution regionsoverlap with each other. After the germanium and boron atoms have beenimplanted in the well 22, a thermal annealing process step is performedto transform the germanium distribution region 26 a to a crystallineregion, and forming the body region 26 and the inverse region 25 withinthe body region 26.

Next, referring to FIG. 6F, a dielectric layer 271 and a conductivelayer 272 of the gate 27 is formed on the top surface 21 a of thecrystalline silicon layer 21′ within the device region 23 a, wherein apart of the body region 26 is located below and in contact with the gate27 in the vertical direction, to serve as the inverse current channel inthe ON operation of the high voltage device 200.

Next, still referring to FIG. 6F, in one embodiment, a lightly dopedregion 281 is formed after the dielectric layer 271 and the conductivelayer 272 of the gate 27 are formed, wherein the lightly doped region281 is for forming a current flowing channel right below the spacerlayer 273, to ensure that the inverse current channel can be formed inthe ON operation of the device. The lightly doped region 281 can beformed by, by for example but not limited to, an ion implantationprocess step which implants N-type conductivity type impurities into thebody region 26 in the form of accelerated ions as indicated by dashedarrows shown in FIG. 6F, to form the lightly doped region 281.

Next, referring to FIG. 6G, a spacer 273 is formed outside the sidewallsof the conductive layer 272, to form the gate 27. The step for formingthe spacer 273 includes a thermal annealing process step. The germaniumdistribution region 26 a is re-crystalized for example by this thermalannealing process step (as indicated by dashed curve arrows shown inFIG. 6G), to become a crystalline region and the body region 26 and theinverse region 25 within the body region 26 are formed at the same time.

Next, referring to FIG. 6H, a body contact 26′, a source 28 and a drain29 are formed below and in contact with the top surface 21 a in thedevice region 23 a. The source 28 and the drain 29 are formed below thetop surface 21 a and in contact with the top surface 21 a in thevertical direction within the device region 23 a, and are located belowand outside two sides of the gate 27 respectively. The source 28 islocated in the body region 26, and the drain 29 is located in the well22, at a location near the right side of the gate 27 (i.e., the sidethat is away from the body region 26). A drift region 22 a is defined inthe well 22 between the body region 26 and the drain 29 in the channeldirection, and is in contact with the top surface 21 a, to serve as adrift current channel in the ON operation of the high voltage device200. The source 28 and the drain 29 have the N-type conductivity type.The source 28 and the drain 29 can be formed by, by for example but notlimited to, a lithography process step and an ion implantation processstep, wherein the lithography process step includes forming aphotoresist layer as a mask, and the ion implantation process stepimplants the N-type conductivity type impurities into the body region 26and the well 22 in the form of accelerated ions, respectively, to formthe source 28 and the drain 29, respectively.

The present invention has been described in considerable detail withreference to certain preferred embodiments thereof. It should beunderstood that the description is for illustrative purpose, not forlimiting the scope of the present invention. Those skilled in this artcan readily conceive variations and modifications within the spirit ofthe present invention. The various embodiments described above are notlimited to being used alone; two embodiments may be used in combination,or a part of one embodiment may be used in another embodiment. Forexample, other process steps or structures, such as a threshold voltageadjustment region, may be added. For another example, the lithographyprocess step is not limited to the mask technology but it can alsoinclude electron beam lithography, immersion lithography, etc.Therefore, in the same spirit of the present invention, those skilled inthe art can think of various equivalent variations and variouscombinations, and there are many combinations thereof, and thedescription will not be repeated here. The scope of the presentinvention should include what are defined in the claims and theequivalents.

1. A high voltage device comprising: a crystalline silicon layer, which is formed on a semiconductor substrate; a well having an N-type conductivity type, which is formed in the crystalline silicon layer; a body region having a P-type conductivity type, which is formed in the well; a gate, which is located on the well and is in contact with the well; and a source and a drain having the N-type conductivity type, wherein the source and the drain are located below, outside, and at different sides of the gate, and are located in the body region and the well, respectively; wherein an inverse region is defined in the body region, between the source and the well; the inverse region serving as an inverse current channel when the high voltage device is in an ON operation; wherein the inverse region includes a germanium distribution region which has a germanium atom concentration higher than 1*10¹³ atoms/cm²; wherein a drift region is defined in the well, between the body region and the drain; the drift region serving as a drift current channel when the high voltage device is in the ON operation; wherein the inverse region further includes a boron distribution region; the germanium distribution region being configured to restrict a diffusion area of the boron distribution region; wherein the body region is formed by following steps: implanting a plurality of germanium atoms in the germanium distribution region via a first ion implantation process step, so that the germanium distribution region has an amorphous region; after the plurality of germanium atoms have been implanted in the germanium distribution region, implanting a plurality of boron atoms via a second ion implantation process step, in a part of the well which includes the germanium distribution region; and after the plurality of boron atoms have been implanted in the well, transforming the germanium distribution region to a crystalline region via a thermal annealing process, and forming the body region and the inverse region within the body region.
 2. The high voltage device of claim 1, further comprising: a drift oxide region, which is formed on and in contact with the drift region; wherein at least a part of the drift oxide region is located below and in contact with a part of the gate; wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure or a chemical vapor deposition (CVD) oxide structure.
 3. The high voltage device of claim 1, further comprising: a body contact having the P-type conductivity type, which is formed in the body region, wherein the body contact serves as an electrical contact of the body region.
 4. The high voltage device of claim 1, wherein the gate includes: a dielectric layer, which is formed on and in contact with the well in a vertical direction; a conductive layer, which is formed on and in contact with the dielectric layer, and serves as an electrical contact of the gate; and a spacer layer, which is formed outside of two sidewalls of the conductive layer, and serves as an electrical insulation layer of the gate. 5.-10. (canceled) 